Vlsi Implementation of Multiplier Based Block Lms Adaptive Filter

17 Abstract— An analysis is made on the computational complexity of Block Least Mean Square Adaptive Filter where the filter computation is decomposed into M sub filters and M=N/L where N is the filter size, L is the block size. The decomposition is done inorder to favour time-multiplexing of the filter output computation and weight-increment term computation of adaptive filter. This structure supports different filter length reconfiguration and has negligible overhead complexity. This scheme also has improved Hardware Utilization Efficiency and even register complexity is independent of its block size. On comparison with the other recently proposed LMS based architectures for adaptive filters, this architecture has L times more multipliers, less adders, almost same number of registers with L times higher throughput.. Different multipliers like Array Multiplier, Wallace tree multiplier, Dadda multiplier and Vedic Multiplier are being compared in the proposed scheme to reduce hardware complexities. Synthesis results shows that proposed scheme has 21.4% lesser area and 3.4 times higher throughput than the existing structures.